If you’ve worked in power electronics, electric vehicles, or high-temperature industrial systems, you’ve likely encountered silicon carbide (SiC) – the material that’s quietly revolutionizing the way these systems operate. As someone who’s spent the last decade running a SiC material and component supply business, I’ve seen firsthand how even the most advanced SiC substrates and devices only reach their full potential if they’re processed correctly. Processing isn’t just a series of steps; it’s the bridge between raw, grown SiC crystals and the high-performance parts our customers rely on. Today, I want to walk you through the core processing techniques we use here to turn raw SiC into something useful, share the lessons we’ve learned along the way, and explain why every step matters for quality and consistency. SiC
Let’s start with the foundation: raw SiC. Unlike silicon, which grows easily into large, uniform ingots from molten silicon, SiC is a compound semiconductor made of silicon and carbon. Its extremely high melting point (above 2,700°C) means it can’t be grown using the same Czochralski method as silicon. Instead, we use physical vapor transport (PVT) to grow large bulk SiC crystals, which are then sliced into wafers. But even a perfect PVT-grown ingot has tiny imperfections – micro-pipes, basal plane dislocations, and stacking faults – that ruin device performance if left unaddressed. That’s where our first set of processing techniques comes in: wafer preparation.
The first step after slicing an ingot is lapping. We use diamond abrasives to grind the wafers flat and remove the rough surface left by the saw. Lapping is critical because it levels out the thin wafers (most are 100-150 microns thick for power devices) and reduces the material loss from subsequent steps. But we’ve learned over the years that lapping pressure matters more than grit size. Too much pressure can introduce new surface damage that’s hard to remove later, so we use a controlled, low-pressure lapping process tailored to each ingot’s dislocation density. For example, wafers from our lowest-defect ingots (which we source only from PVT crystals grown in our own clean rooms) use 30-micron diamond grit, while higher-defect wafers use smaller grits to avoid cracking.
Once lapped, we move on to polishing. SiC is one of the hardest known materials (9.5 on the Mohs scale, second only to diamond), so standard silicon polishing methods don’t work. We use chemical mechanical polishing (CMP) for the final wafer finish, which combines a soft polishing pad with a chemical slurry that etches the SiC surface while mechanical action removes the damaged layer. The key here is the slurry composition. We’ve tested dozens of slurries over the years – some use silica, some use alumina, some add oxidizing agents – and found that a colloidal silica slurry with a mild hydrogen peroxide oxidizer gives us the lowest surface roughness (below 0.1 nm Ra) without introducing contamination. Contamination is a big no here; even a single metal particle on the wafer can cause a short circuit in a power device, so our CMP process is done in a class 100 clean room, with regular checks for trace metals using X-ray fluorescence.
After polishing, the wafers go through epitaxy – the process of growing a thin, high-purity SiC layer on top of the polished wafer. This is arguably the most important step for device performance, because the epitaxial layer is where the actual power switch or diode is built. We use two main epitaxy methods in our facility: chemical vapor deposition (CVD) and physical vapor deposition (PVD), though CVD is by far the most common for high-power devices. For SiC CVD, we use a reactor that heats the wafer to 1,600°C, then flows a mixture of silane (SiH₄) and propane (C₃H₈) over it, along with a dopant gas (nitrogen for n-type, aluminum for p-type) to adjust the layer’s conductivity. The growth rate is carefully controlled – usually between 1 and 5 microns per hour – because too fast means uneven layers, too slow increases cost and defect risk.
We’ve invested heavily in our epitaxy reactors because this is where a lot of our customers’ biggest pain points come in. One of the most common issues our customers face is basal plane dislocations (BPDs) in the epitaxial layer, which can lead to bipolar degradation in power diodes over time. To reduce BPDs, we use a “buffer layer” in our CVD process – a thin, low-doped SiC layer grown at a slightly lower temperature that acts as a filter for dislocations coming from the substrate. We also do in-situ doping control, using real-time gas monitoring to adjust the dopant flow so the layer’s conductivity is consistent across the entire wafer, even across 150mm diameter wafers (the standard now for large-scale production).
Once we have high-quality epitaxial wafers, we move on to device fabrication – turning those wafers into actual power components like MOSFETs, JFETs, and Schottky diodes. SiC device fabrication shares some steps with silicon processing, but the material’s hardness and reactivity mean many steps are tweaked, and some are entirely different. The first big step is photolithography, where we pattern the wafer with a layer of photoresist to define where we’ll implant dopants. But SiC is transparent to UV light, which makes standard photolithography hard. So we use deep UV (DUV) photolithography, which uses shorter wavelengths (248nm) to create sharper patterns on the SiC surface. We also use hard masks (like silicon oxide or nitride) instead of photoresist for some layers, because photoresist can be damaged by the high temperatures used in subsequent processing steps.
Next is ion implantation, which we use to dope specific regions of the device – like the source and drain of a MOSFET. SiC has a high stopping power for ions, so we need to use high-energy implanters to get dopants deep enough into the epitaxial layer. For example, to dope the drain region 1 micron below the surface, we use nitrogen ions accelerated to 1 MeV. But ion implantation creates damage in the crystal lattice, so after implantation, we do a high-temperature annealing step at 1,700°C to repair that damage and activate the dopants. That’s another key difference from silicon, where annealing is usually done at around 1,000°C. The high-temperature annealing is tricky, though – if the temperature is too high, the dopants can diffuse too much, blurring the patterns; if it’s too low, the lattice damage remains, leading to poor device performance. We use a rapid thermal annealing (RTA) process with inert argon gas, holding the wafer at 1,700°C for just 30 seconds, which gives us the perfect balance of damage repair and minimal diffusion.
After implantation and annealing, we add metal contacts to the device. SiC’s chemical inertness makes it hard to bond metal to, so standard aluminum or gold contacts don’t work well. For n-type SiC, we use a nickel contact that forms a silicide (NiSi) when heated, creating a low-resistance ohmic contact. For p-type SiC, nickel contacts work too, but we often add a layer of gold on top for better wire bonding, since aluminum wire bonds to nickel can have higher resistance at high temperatures. We do the metal deposition using physical vapor deposition (PVD) – either e-beam evaporation or sputtering – and pattern the metal using liftoff photolithography, where we coat the wafer with photoresist, expose the contact pattern, then deposit the metal and dissolve the photoresist to leave only the desired metal traces.
Once the devices are fabricated, we have to test and package them. Testing is a critical quality control step – we use probe stations to test each individual die on the wafer for breakdown voltage, on-resistance, and leakage current, sorting out any defective parts before packaging. For packaging, we use two main formats: die for customers who do their own packaging, and finished modules for those who want a turnkey solution. SiC packaging has its own unique challenges, too – SiC devices can operate at junction temperatures up to 200°C, much higher than silicon’s 150°C limit, so we use high-temperature substrates like aluminum nitride (AlN) for the base of the package, which has high thermal conductivity and matches the coefficient of thermal expansion (CTE) of SiC, reducing stress when the device heats up. We also use sintered silver for die attach instead of solder, because solder can melt at high temperatures, while sintered silver has a melting point above 900°C. We’ve seen too many customers use standard silicon packaging for their SiC devices and run into reliability issues, so we always work closely with them during the design phase to make sure their packaging is optimized for SiC.
Over the years, we’ve learned that processing SiC is as much about consistency as it is about individual steps. A small variation in lapping pressure, a 10°C shift in epitaxy temperature, or a 5-second change in annealing time can make the difference between a device that works perfectly for 10,000 hours and one that fails after 100. That’s why we’ve invested in in-process monitoring tools that track every step of production, from ingot growth to final testing. We also do 100% incoming material inspection, working only with trusted suppliers for raw materials and our own in-house grown PVT crystals, to eliminate variability at the source.
At the end of the day, our goal as a SiC supplier isn’t just to sell wafers or devices – it’s to give our customers parts they can rely on, whether they’re building electric vehicle inverters, solar inverters, or industrial motor drives. If you’re working on a project that requires high-performance SiC components, and you’re looking for a supplier that prioritizes quality, consistency, and collaborative support, we’d love to connect. We can work with you to understand your specific needs, whether that’s custom epitaxial layers, specialized device designs, or packaging tailored to your application.
To learn more about our SiC processing capabilities or to discuss your project, feel free to reach out to our team for a consultation. We’re here to help you get the most out of SiC technology, and we’re committed to providing the highest quality materials and support every step of the way.
Off-grade Silicon References
- Kimoto, T. (2015). "Fundamentals of SiC Power Devices." IEEE Transactions on Electron Devices, vol. 62, no. 3, pp. 615-627.
- Powell, J. A., & Rowland, L. B. (2002). "SiC Materials and Devices." Proceedings of the IEEE, vol. 90, no. 6, pp. 969-986.
- Zhang, X., et al. (2020). "Advances in Silicon Carbide Epitaxy for Power Electronics." Journal of Crystal Growth, vol. 540, pp. 125637.
- Matocha, K., et al. (2018). "Reliability of SiC Power Devices in High-Temperature Applications." Microelectronics Reliability, vol. 88, pp. 1027-1033.
- Sudarshan, T. S., & Das, S. (2007). "Metal Contacts to Silicon Carbide: A Review." Materials Science and Engineering: R: Reports, vol. 55, no. 1-2, pp. 1-60.
Anyang Baitengxin Metal Co., Ltd.
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